1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a dynamic semiconductor memory device capable of performing a refresh operation independently of input signals from the outside (which will be referred to as a “complete-hidden-refresh-function-included DRAM” hereinafter).
2. Description of the Background Art
In a field of portable terminals such as mobile phones, there is widely adopted an asynchronous general-purpose static semiconductor memory device (which will be referred to as a “SRAM” hereinafter) for which external clocks need not be supplied. In the SRAM, the refresh operation is unnecessary. Therefore, the memory can be accessed without having to wait until the refresh cycle finishes, and a complex control thereof is not needed. Thus, the system configuration can be simplified by using the SRAM. For this reason, the SRAM was suitable for use with the portable terminal.
Recently, however, the function of the portable terminal has been improved significantly, and even the portable terminal comes to require a large-capacity memory function. The SRAM has a memory cell size which is about 10 times larger than that of a dynamic semiconductor memory device (which will be referred to as a “DRAM” hereinafter). Thus, the cost for a chip will significantly be increased to make an SRAM with large capacity. For this reason, there has been an idea to use the DRAM having a lower cost per unit bit of memory in place of the SRAM in the portable terminal.
The DRAM, however, requires a complex memory control for performing the refresh operation. For portable-terminal manufacturers that have been engaged in design of systems using SRAMs as memories, it is therefore not easy to use DRAMs as substitutive memories of SRAMs.
Under these circumstances, each semiconductor manufacturer has begun the development of a new semiconductor memory device which is the DRAM in nature but operates as the SRAM externally. This new semiconductor memory device is reported in the publication of Kazuhiro Sawada, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 23, No. 1, February 1998, (pp.12–19).
For this new semiconductor memory device, the same internal memory cells as those used in the DRAM are used. On the other hand, external interfaces such as control signals and address signals input to the semiconductor memory device are the same as those of the SRAM. Different from the refresh operation or self-refresh operation of the conventional DRAM, the refresh operation of the new semiconductor memory device is not controlled by signals received from the outside. Rather, the refresh operation is performed based on a refresh command signal /REFE periodically output from a refresh circuit provided within the semiconductor memory device. The refresh circuit includes a timer circuit which is a ring oscillator, and outputs the refresh command signal /REFE in response to a cycle signal periodically output from the timer circuit. The timer circuit continuously outputs the cycle signal.
Based on that function, the new semiconductor memory device as described above will be referred to as a “complete-hidden-refresh-function-included DRAM”. The development of the complete-hidden-refresh function-included DRAM enables an adaptation to a higher-performance portable terminal.
The complete-hidden-refresh-function-included DRAM selects an operation state or a standby state by an external signal. The operation state is a state in which a write or read operation can be performed. The standby state is a state in which the write or read operation is not performed. It is to be noted that, the refresh operation is performed regardless of the standby state or the operation state.
In normal operation, the write or read operation is performed in the operation state. There may be a situation, however, wherein the write or read operation is still performed when the operation state is terminated by a signal from the outside. In such situation, if the write or read operation is terminated because of the termination of the operation state, the accurate write or read operation will not be possible.